Modern high-end integrated circuits (ICs) are known to consume high current in a wide frequency range which has to be reliably provided by the IC power supply in order to ensure IC functionality. Therefore, power supply and its distribution is a critical item in high end electronic designs that need to fulfill ambitious requirements with respect to reliability and low impedance. In particular, the IC's power supply network structure has to reliably provide sufficient power in each individual load location within the system. A variety of power domains need to be taken into account, and stable supply voltage levels have to be ensured at each load, independently of actual current demand. Design and implementation is complex and requires deep insight into high frequency behavior of board design and package design. In order to provide the desired functionality for the IC under consideration, there is a need for a methodology to determine whether the actual power distribution within the IC is equivalent to what is required to meet certain design requirements.
Very large scale integration (VLSI) chips designed for use in high end servers are typically equipped with a number of self test mechanisms, such as MBIST (memory built-in self-test), LBIST (logic built-in self-test) etc., that permit the integrated circuit to test itself. Self-testing is used to enable faster and less expensive manufacturing test as well as provide quality checks during operation. The IC chip is supplied with a self-test function that verifies all (or parts of) the internal functionality of the IC. This IC self-test function may be carried out as part of a system self-test that checks RAM and buses during system power-up.
While there are a number of known self-testing methods that cause an IC to test the integrity of its own circuitry or signal integrity, up to now there is no self-test that covers the functionality of the individual power supply at one or more VLSI chip locations.
One present day approach for investigating power supply quality with the chip uses static (DC) load elements to emulate a stimulus for the power supply. Another approach is based on conducting on-chip power supply noise measurements during chip operation with a large number of possible load scenarios. These solutions, however, have a number of drawbacks. For one thing, they require dedicated on-chip power supply measurement setups for each VLSI chip location, with each load scenario requiring its own specific measurement. Additionally, they offer no support for power supply optimization during system design and yield no statement about power supply degradation over system lifetime. Moreover, they furnish no information on malfunction/degradation of discrete power supply components or on partial breakdown of redundant power supply connections. In addition, they require two pins (VDD and GND) to be provided in each specific location within the chip destined for power supply measurements.
U.S. Pat. No. 7,203,608 discloses a method for impedance measurement of a chip within a design by measuring on-chip voltage values in the time domain and performing a Fourier transformation to obtain a measurement of the voltage in the frequency domain. The method makes use of a pseudo impulse current which is difficult to create and control. Moreover, the method described in U.S. Pat. No. 7,203,608 requires measuring switching charge during impulse current, which is complicated to implement and error-prone.
U.S. Pat. No. 6,768,952 describes a method for periodically toggling clock frequency in a chip, generating a periodic current waveform, and conducting a set of voltage measurements. In order to implement this method, the system requires a reset state. Moreover, multiple discrete clock frequencies are used and evaluated. This requires multiple measurements and thus is quite elaborate.
Thus, there is a need for a simple and efficient self-test method for assessing power supply quality and distribution at one or more VLSI chip locations.